Analysis of High Speed Radix-4 Serial Multiplier

Multiplication is the most essential operation in digital signal processing, artificial intelligence, neural networks, and machine learning. In the VLSI domain, the performance of electronic devices depends on area, power, and delay. This paper brings the idea of a modified high-speed Radix-4 serial multiplier which multiplies two signed numbers with more speed and consumes less power. In this proposed multiplier, booth encoding is used to reduce the number of bits in the multiplier part of the multiplication process. The improvements are made in the addition of generated partial product as well as in the final addition part to get the multiplication output with more speed. To add partial products, carry save adder is used, and to add the final two rows of the multiplication process Kogge stone adder is used to improve the speed. A 32-bit multiplier is designed and coded in Verilog HDL, and further it is simulated using Xilinx ISE, and synthesized using the genus synthesis tool in 45nm Technology. The performance of the proposed multiplier is compared with the existing serial multiplier in terms of area, power, and delay. The comparison result shows that the proposed multiplier has an improvement of 31.09% in speed and at the same time a reduction of 5.31 % in power overhead as compared to the existing multiplier.