Exploration of Negative Capacitance in Gate-All-Around Si Nanosheet Transistors

Gate-all-around (GAA) nanosheet (NS) field-effect transistors (FETs) are the most promising candidates to replace FinFETs and nanowire (NW) FETs in future technology nodes owing to their improved short-channeleffects, high current drivability per layout footprint (LF), and extreme scalability. The much-needed voltage scaling in these aggressively scaled devices can be provided by introducing negative capacitance (NC) effect, which results in sub-60 mV/decade switching behavior. In this article, we explore how NC effect manifests into silicon NS transistors by using technology computer aided designs (TCAD). The NC effect originates from a metal-ferroelectric-metal- insulator-semiconductor (MFMIS) configuration in the gate-stack. The performance of single channel NC-NSFET is benchmarked against NC-NWFET and NC-FinFET of comparable device dimensions. NC-NSFET shows 9% and 38% lower subthreshold swing when compared to NC-NWFET and NC-FinFET, respectively. For NC-NSFETs, capacitance matching, between the ferroelectric (FE) and the underlying MOS capacitance, is achieved with a thinner FE layer. Between single stack and double stack devices, single stack NC-NSFET offers faster switching at low operating voltages. Within a stack, nonuniformity in NS cross sections is found to influence device behavior. We also report the performance of NC-NSFETs in terms of key device design parameters, like channel length, thickness, and width of NS, and metal work function (WF), where, thinner NSs and metals with high WF provide significant enhancement in I
_on
/I
_off
ratio. The results presented here can aid in the design, operation, and performance improvement of emerging NC-NSFET devices.