Current steering high-speed DAC: architecture analysis and simulation results

A DAC architecture based on the current steering method is presented. The proposed architecture exploits the oversampling and uses a MASH like configuration. The DAC requires to use two current steering 5-bit D/A converters whose current references are properly scaled. The two output currents are summed at the output node to achieve the output signal. With an oversampling factor equal to 8 and 40 MHz band-width (clock frequency 640 MHz) it is possible to reach an SNR as large as 72 dB.