Timing Reliability Improvement of Master-Slave Flip-Flops in the Presence of Aging Effects

Manufacturing process variations and transistor's aging effects are two major concerns for reliable design of nano-scale digital circuits. Correct functionality of flip-flops (FFs), as one of the most important elements in digital circuits, plays a key role in reliability of modern circuit designs. In this paper, a timing reliability improvement technique is proposed for master-slave FFs considering the impacts of process variations and aging effects. In this technique, the internal circuitry of the FF is restructured in order to improve the reliability by reducing the stress time (i.e. the time of being ON) of the transistors which are stacked in the feedback loop. Using Monte-Carlo based HSPICE simulations, the efficacy of the restructuring-based reliability improvement technique is shown considering various experimental conditions (i.e. different process variation ratios and lifetime values). The experimental results show that, the lifetime reliability of Master-Slave FFs improved by 22% in expense of 3% area overhead, 8% propagation delay absolute change, and 6% absolute power change in the presence of 20% variation ratio and 9 years of operation time.