Thermal Modeling and Design of 3D Memory Stack on Processor with Thermal Bridge Structure

Proper thermal design and evaluation of 3D stacked IC packages remain to be a key challenge. This is especially the case if the underneath die in the stacked package is large in size with high power dissipation, which is typical for a processor allocated under the memory stack. In this work, a novel thermal bridge structure is introduced to address the thermal management of stacked die package piled with memory chips on processor, which is then connected to the metal lid and heat sink. The thermal issues associated with the package are highlighted and then the enhanced thermal performance of the present package with thermal bridge is demonstrated through numerical modeling. Numerical results show that both the on-chip temperature and temperature difference can be minimized significantly with the thermal bridge structure. For the bump cases investigated, the case of bump(50,30) provides the lowest processor temperature with the lowest temperature level. Thermal bridge with high thermal conductivity is more favorable at the smallest bump case with the lowest bump thermal resistance. Finally, it is pointed out that there exists an optimal range of thermal resistance ratios, at which the minimum temperature difference can be achieved on the processor.