Architecture Design of Distributed Redundant Flight Control Computer Based on Time-Triggered Buses for UAVs

With the rapid development of unmanned aerial vehicles (UAVs) performance and their increasingly complex tasks, the current centralized flight control computer (FCC) architecture based on the event-triggered mechanism cannot meet the requirements of openness, reliability, and real-time processing. In view of the development trends and technical requirements of future UAVs, a distributed redundant FCC architecture design method based on commercial off-the-shelf (COTS) technology and a set of dual-channel redundant time-triggered buses is proposed. With this architecture, new UAV flight control design methods are then proposed, such as distributed fault-tolerant management, Byzantine fault-tolerant design based on dual-core self-monitoring, and an open/integrated design method for airborne multi-sensor information processing and fusion. According to the characteristics of the redundant FCC based on the time-triggered buses, a distributed task scheduling and communication model is established, and an optimal static scheduling and real-time analysis algorithm of distributed tasks based on a search tree is proposed. Finally, the real-time performance and reliability of the FCC are analyzed and verified. The verification results show that, compared with the centralized FCC architecture based on the event-triggered mechanism, the proposed UAV FCC architecture has better task schedulability and system scalability. Moreover, it has a higher task reliability under the same redundancy configuration, which means that it can provide a distributed, synchronous fault-tolerant and redundant reconfigurable technology platform for future UAV FCCs.