A 65.5-dB SNDR 8.1–11.1-nW ECG SAR ADC With Adaptive-Latching OSC-Based Comparator and DAC Calibration

This letter presents a 65-dB SNDR ECG SAR analog-to-digital converter (ADC) that utilizes a VCM-based LSB-first switching scheme for extraordinary low-power operation under low supply voltage. Unlike conventional VCO-based or OSC-based comparators which being either power inefficiency or low speed, the adaptive-latching OSC-based comparator is presented. It achieves low power while simultaneously maintaining an adequate speed under a low supply voltage through the adaptive latching scheme and asynchronous operations. The switching scheme incorporating the proposed comparator also facilitates the DAC mismatch calibration, where no additional analog hardware is necessary for the DAC mismatch detection. After calibration, the worst INL decreases from 2.6 LSBs to 0.85 LSB. The prototype, fabricated in 65-nm LP CMOS, attains 65.48-dB SNDR at 4 KS/s with an OSR = 4 while consuming only 8.1 nW at 0.55-V supply and leading to a 173.4-dB Schreier FoM.