A Highly Efficient 60 GHz CMOS Doherty Power Amplifier With Adaptive Gate Biases

In this paper, a Doherty power amplifier (DPA) in 65 nm CMOS process at 60 GHz is presented. In the proposed design, both the gate biases of carrier and peaking amplifiers are adaptively controlled according to input power levels. Different bias control schemes are applied for the carrier and peaking amplifiers respectively to achieve efficient Doherty operation and improve efficiency. Power detectors are applied to achieved the dynamic bias voltages and consumes very low power. By combining active load modulation and the adaptive biases, both the back-off and saturation power added efficiencies (PAEs) of the DPA are enhanced and the gain compression point is extended. Simulated results show that the 20% saturation PAE and 13% 6-dB back-off PAE are achieved, and the output 1-dB gain compression point (OP1dB) is around 17 dBm.