Understanding the Effect of Stress on Surface Roughening during Silicon Spalling: A Theoretical and Experimental Study

Spalling has been proposed as a promising kerfless technique for slicing thinner wafers (down to 5 μm) and thus enhance the wafer yield from an ingot. The main challenge of spalling is to control the roughness and thickness variation of the spalled wafers that can be as high as 100% of the wafer thickness. The roughness affects the mechanical stability (due to surface defects) as well as the effective minority carrier lifetime (surface recombination velocity). In this paper, we have developed a dynamic finite element analysis to correlate the surface roughness of a spalled silicon wafer with the stress applied at the crack tip. These predictions were experimentally validated with crack velocity measurements and surface roughness analysis for different applied stresses. By controlling the stress applied, we were able to reduce the surface roughness in silicon by 62%.