Delay and Area analysis of hardware implementation of FFT using FPGA

The hardware realization of fast fourier transform (FFT) consists of complex arithmetic operations such as multiply and accumulate. The key idea of this paper is to implement the 8-point Radix-2 DIT (Decimation In Time) FFT. In the FFT algroithm the twiddle factor generation by traditional method of generating sine and cos is replaced by the CORDIC algorithm for trigonometric functions. For the multiply and accumulate unit, different multipliers were used namely CORDIC multiplier, Single precision floating point multiplier. The adder blocks used in the implementation are linear adders such as Ripple Carry Adder (RCA) and parallel prefix adders such as Kogge-Stone Adder (KSA). Different combinations of multipliers and adders are used in the implementation of FFT, using VHDL in VIVADO 2016.2 version and programmed it in Xilinx ZYNQ FPGA board. The FFT implementation using single precision floating point multiplier incorporated with CORDIC multiplier and koggestone adder gives better delay performance compared to other combinations. In terms of area the combination of CORDIC multiplier with Ripple carry adder performs best.