A Technique of Designing Low Leakage SRAM in Deep Sub-micron Technology

SRAMs are extensively used in system-on-chip (SoC) designs. Embedded SRAMs occupy a majority of the die area leading to increased power consumption. Although the performance of SRAM in finer technologies has remarkably improved, still read/write failures and leakage power dissipation are major concerns at nanometer regime. In this paper, a low leakage SRAM cell is proposed based on a source-biased inverter. The source biased inverter that uses two extra transistors to mitigate the leakage current gives a leakage power savings of 67% compared to the conventional inverter. The source biased inverter is then used to replace the two inverters in 6T SRAM cell in 32nm CMOS technology. The proposed low leakage 10T SRAM cell gives a leakage power savings of 86.24% as compared to the 6T SRAM cell. The stability of the proposed low leakage 10T SRAM cell is comparable with the standard 6T SRAM cell.