Transposed 3 Tap FIR Filter Design Using Consolidation of Pipelining and Parallel Processing Technique

The speed of the DSP processor mainly depends on the execution time of the data path and memory elements. The main objective of the paper is to reduce the critical path of the system and trying to increase the speed. The combined pipelining and parallel processing technique is applied to the 3 tap fir filter. The proposed 3 tap transposed FIR filter with combined pipeline and parallel process gives a 31.33 % improvement in power delay product compare to conventional designs. The proposed technique is operated at different supply voltages and simulation results are verified with cadence software.