Design and Development of Concurrent Architecture Based Differential Protective Relay on FPGA

Relay is first line of defense of any Power Protection System. Relay send signal to circuit breaker if any abnormal activity found in system and as soon as circuit breaker detects abnormal behaviour of the system it disconnect the faulty part from the system for proper functioning of the system minimize the loss to the active system. Initially researchers implemented various relay with help of microprocessor due to flexibility and programming approach. But drawback of this approach is its speed as sequential implementation. In this paper concurrent architecture based differential relays implemented on Virtex 5 XC5VLX50T FFG1136C FPGA board. The results are communicated to UART interface. Baud rate of the serial communication can be achieved with help of clock divider circuit. The pipeline architecture of the FPGA improves speed and efficiency of the relay. Differential relay is implemented with help of VHDL programming and IP cores.