Design of a Two-Step Low-Power and High-Speed CMOS Flash ADC Architecture

Analog-to-Digital Converters (ADC) are very important components in the modern digitized world for the processing of analog signals. ADCs, find a wide range of applications in signal processing, communication systems, and embedded systems. In this paper, an architecture for low-power and highspeed CMOS flash ADC is presented. The proposed design is implemented using 180 nm CMOS technology. The concept of most significant bit (MSB) generation with a switched reference voltage is employed. A control circuit has been designed for switching the reference voltage around mid-point voltage (V
k
) with respect to the input signal. The present design requires 2
^N-1
comparators in comparison to 2
^N
- 1 comparators of conventional flash ADC. In addition, a low power encoder has been used in the proposed flash ADC. A 6-bit flash ADC has been designed and performance is analyzed with the simulation results. For the verification, the flash ADC is operated at 1 MHz, and it consumes a total power of 604 microwatt.