A Decimal Multiplier With Improved Speed Using Semi-Parallel Iterative Approach

This paper presents a semi-parallel iterative decimal multiplier. The Proposed multiplier uses BCD-8421 encoding which does not require any recoding as compared to all the implementations reported in the literature. It employs semi-parallel partial product generation for faster multiplication, decimal 4:2 adder for partial product reduction and a novel iterative partial product reduction approach. The proposed design is implemented and verified using FPGA, the results of the implementation show that the proposed semi-parallel iterative design performs better with lesser delay than other decimal multipliers and binary multipliers with double precision that have been reported in literature.