Neural Network Based Design Optimization of 14-nm Node Fully-Depleted SOI FET for SoC and 3DIC Applications

In this article, by using neural network, we proposed a method to optimize Fully-Depleted (FD) Silicon-on-Insulator (SOI) Field-Effect-Transistor (FET) structures to maximize the on/off current ratio for 14-nm node (70-nm Gate Pitch) System-on-Chip (SoC) and sequential 3-dimensional integrated circuit (3DIC). Using machine learning method, the neural network accurately predicted the electrical behaviors of 14-nm node FDSOI FETs. Also by using backpropagation and gradient descent method, the device structures were modified to improve on/off current ratios for high performance (HP), low operating power (LOP), and low stand-by power (LSTP) applications. These optimized structures were secured within the process range of conventional FDSOI FETs. Among the optimized parameters, drain-side spacer length (L
_spd
), source/drain junction gradient (L
_sdj
), and thickness of source/drain epi (T
_sd
) showed different behaviors for each application and thickness of buried oxide (T
_box
) was maximal in optimization results. The detailed physical analysis was conducted to evaluate these parameters for each application. The neural network based optimization was powerful and efficient while saving time and cost in device design.