Regulation Control Design Techniques for Integrated Switched Capacitor Voltage Regulators

This paper presents and comprehensively compares various regulation control design techniques targeted to improve output voltage ripple, droop against load transients, and power efficiency of a 2:1 switched-capacitor voltage regulator (SCVR). Three unique SCVR schemes are designed in 40nm CMOS that provide enhanced tradeoffs over the baseline design. First, we present the divided reference slice scheme, which achieves the least droop (27.95 mV) and quickest recovery of 600 ps across a 10X load step. Second, the switch width modulation scheme is proposed to help in power reduction proportional to the load current. Third, a header-footer based current-mode control design scheme is presented which achieves up to 2X reduction in output voltage ripple compared to the baseline scheme. A peak efficiency of 87.6% is achieved at a load current of 44 mA.