All-Digital Time Integrator Using Bi-Directional Gated Vernier Delay Line

This paper proposes a bi-directional gated Vernier delay line (BDGVDL) all-digital time integrator particularly suitable for all-digital ΔΣ modulators. The proposed time integrator features full compatibility with technology scaling, a high resolution, rapid integration, moderate power consumption and silicon area requirement, and built-in digitization. The principle and design considerations of the time integrator are detailed. The time integrator is designed in a TSMC 130 nm 1.2 V CMOS technology and analyzed using Spectre with BSIM4 device models and its functionalities are validated using simulation results.