Verification of Power-based Side-channel Leakage through Simulation

Side-channel resistant design is becoming a common requirement in IC design for connected systems and Internet of Things. In contemporary design practice, power-based side-channel leakage is validated on a fabricated chip by an independent security testing team. This practice is expensive. There is a need for a design methodology and an associated design flow to perform validation of power-based side-channel leakage during the design flow and before chip fabrication. We describe the technical requirements for this approach, and we summarize the state of the art. We then describe the side-channel leakage verification in a System-on-Chip, and we compare simulations with measurements from a fabricated chip of the same design.