0.78-mW/pF/GHz, 12.5-GHz Quadrature Resonant Clock with Frequency Tuning Capacitor

This paper presents a quadrature resonant clock generator with tuning capacitors for driving four 2.1-mm load wires. By using frequency tuning capacitors, which reduce the mismatch in operating and LC resonant frequencies, the proposed clock generator offers power reduction by 19-22% compared with conventional CMOS clock driver and by 1632% compared with conventional CML clock driver. Measurement result from the prototype chip fabricated in 65 nm CMOS shows that total power consumption of the proposed quadrature resonant clock is 14.5 mW in 12.5-GHz operation with four 370-fF load wire capacitances. Measured phase noise at 1 MHz offset is -141.36 dBc/Hz.