A High Power Low Dropout Voltage Regulator Design with an Enhanced Resistive Bank Circuit for Powering an RF IC for DSRC Applications

This paper presents a high power Low Dropout Voltage Regulator Design with an enhanced resistive bank circuit for powering an RF IC for DSRC applications. Due to the addition of the enhanced resistor bank circuit, the feedback takes part in the amplified output from the input, such that the gain is controlled much more by the feedback network. A low pass filter is used to remove excess noise. The quiescent current of the proposed LDO structure is reduced to 3.85 μA from a 3.3 V supply voltage, to improve the power efficiency of LDO. Phase Margin of the bandgap reference circuit is 62.30°. For a load current of 100 mA settling time of 26 μs is achieved by the proposed LDO. PSRR of -46 dB is achieved till 1 kHz of frequency. Line regulation and Load regulation of the proposed LDO is 30.6 mV/V and 0.278 mV/mA respectively. This structure is implemented using 130 nm Bipolar-CMOS-DMOS (BCD) technology with an active area of 206 μm × 161 μm.