An On-Chip Ultra-Low-Power Hz-Range Ring Oscillator Based on Dynamic Leakage Suppression Logic

In this paper, simulation and experimental results of an ultra-low-power Hz-range ring oscillator are presented. The proposed circuit can operate from subthreshold voltage (0.24 V) to nominal voltage (1.8 V) and reaches power consumptions in the picowatt order. The design, based on Dynamic Leakage Suppression (DLS) logic, has been implemented in 0.18 um CMOS technology and uses sub-pF capacitors. Its main features are its low power consumption, small area, wide supply voltage range and utmost simplicity.