Using Reduced Graphs for Efficient HLS Scheduling

High-Level Synthesis (HLS) is the process of generating digital circuits from high-level algorithmic descriptions. One of the major steps in this design approach is scheduling, which uses the Control/Data Flow Graph (CDFG) of the software code and determines in which order operations must occur. Traditionally, the scheduling process is time and memory intensive. In this paper, we present a new approach to replace the conventional scheduling portion of the HLS tool chain. This new technique significantly reduces the complexity of scheduling, resulting in improved memory usage and lower computational effort. The results demonstrate that an average 16 times speedup on the time required to determine the schedule can be achieved, with just a fraction (1/5 on average) of the memory usage, and with only 0 to 6% of added cost on the final hardware execution time.