A Low-Cost and High-Throughput NoC-Aware Chip-to-Chip Interconnection

To offer sufficient computing capability, current hardware systems tend to be equipped with multiple chips, while each chip integrates tens to hundreds of cores with Network-on-Chip (NoC) architecture. Thus, chip-to-chip interconnection for NoCs becomes indispensable. However, state-of-the-art inter-chip interconnection, like PCIe or SRIO, suffers from latency and bandwidth bottlenecks especially for communication-intensive tasks. In this paper, we propose a NoC-aware chip-to-chip interconnection scheme. In addition to a lightweight interconnection architecture and protocol, we utilize NoC routers to improve inter-chip connection. A virtual-channel router with transmission priority in the NoC is proposed to eliminate the congestion in the chip-to-chip interconnection. The interconnection system is implemented in Verilog RTL and verified on the Xilinx ZCU102 evaluation kit, achieving up to 10Gb/s/lane line rate with low resource utilization.