FILA: Fault-Model for Interconnection Links in Application-Specific Network-on-Chip Design

In the nano-scale era, to improve the system reliability the major challenge is to predict the NoC component failures in runtime and propose an efficient technique. To predict the failures in runtime, probabilistic based models have been proposed in the literature. However, these techniques provide an empirical model to predict failure. Hence, there is a need for the dynamic fault-model that predicts the runtime failures in NoC design. This paper presents a novel fault-model for the interconnection links in application-specific Network-on-Chip (NoC) design. The proposed model acts as a baseline reference to predict the faults during the runtime of an application on NoC. The experimentations have been carried for different widths of the interconnection links by providing application-specific traffic patterns. The results show that the meantime to failure of an interconnection links having width of 0.3 μm, and 1 μm getting reduced with increase in the link bandwidth.