A 65nm Logic-Compatible Embedded and Flash Memory for In-Memory Computation of Artificial Neural Networks

In-memory computing using zero standby power nonvolatile memory is an attractive candidate for processing massively-parallel dot-products in artificial neural networks with high energy efficiency. A logic-compatible embedded flash (eFlash) is one of such nonvolatile memories. It has several advantages over the other candidates for in-memory computing: (1) programmable multi-level weight storage, (2) low power consumption with zero standby current, (3) low-cost fabrication using logic-process. Prior work proposed a 5T NOR-type eFlash cell for processing dot-products that are essential for neuromorphic computing. Despite the reliable dot-product computation using its carefully-designed program-and-verify sequence, the low memory density due to its 5T bitcell structure is one of the remaining challenges. In this work, we propose an AND eFlash cell structure for in-memory computation of artificial neural networks (ANNs) using multiple eFlash bitcells and shared access transistors. The proposed AND eFlash cell array is used for computing dot-products between binary inputs and reconfigurable bit-precision weights. The bitcell area has been reduced by 15% for the triple-cell structure compared to the prior 5T NOR eFlash. A multi-cycle program-and-verify operation is used to calibrate and improve the linearity.