A 0.45-V Low-Power Image-Rejection Low-Noise Amplifier in 0.18-μm CMOS Technology

A low-power image-rejection LNA by using TSMC 0.18 μ m CMOS process under 0.45-V supply voltage has been proposed. For low-power application, forward body biasing and folded topology are proposed. A feedback capacitor is utilized to reduce the size of the inductors for achieving low power consumption and small chip area. Moreover, a resonant LC tank has been developed for realizing gain enhancement and image rejection simultaneously. The measured results show power gain, noise figure, IIP3 and are 16.5 dB, 3 dB, and −16 dBm at 2.6 GHz, respectively. The measured IRR is 26 dBc at 4.3 GHz. The measured power consumption is 0.6 mW.