A Low-Power 65/14nm Stacked CMOS Image Sensor

This paper presents a low-power stacked CMOS image sensor (CIS) in 65/14nm process. With 14nm process, we could achieve 29% less power consumption than the conventional CIS in 65/28nm process. The measured random telegraph noise (RTN) result shows the 65/14nm stacked CIS to guarantee the commercial sensor image quality even though a fin field-effect transistor (FinFET) process is three-dimension channel structure. The pixel array of the implemented chip consists of 12-mega pixels (Mp) with a dual-photodiode (2PD) in 1.4μm pixel pitch, and the sensor output provides 120 frames per second while it consumes 612mW for 12Mp image and 3Mp auto-focus data via a mobile industry processor interface (MIPI) physical layer (DPHY) up to 6.5Gbps/lane. The measured random noise is 2.2e-at 16× analog gain, and figure-of-merit (FoM) of analog-to-digital converters (ADCs) achieves 0.46e-nJ.