Hardware Implementation for High-Speed Parallel Adder for QSD 2D Data Arrays

In this paper, a fast parallel 2D-array computation has been implemented based on QSD number system and FPGA hardware. The QSD numbers are coded in binary bit streams in order to be processed inside the digital hardware. The same parallel addition algorithm for adding two QSD numbers is used for adding the binary codded QSD numbers and its two steps has been implemented successfully in FPGA chip. The syntheses and implementation of the hardware parallel adder shows that the proposed parallel adder has a high performance than the software version, and the size of data arrays depends on the number of logic elements of the FPGA chip.