Asymmetric dynamic Avalanche during turn-OFF in paralleled IGBT Chips under Long Term Testing Conditions

The dynamic avalanche can cause robustness issues due to dynamic current filaments leading to locally increased thermal stress during turn-OFF and therefore limits the safe operation area of IGBTs. Long term repetitive IGBT measurements under dynamic avalanche conditions have shown shifts of the IGBT’s switching behaviour. Further it has been shown that dynamic avalanche can cause current imbalances between paralleled IGBTs. The Objective of this paper is a further understanding of the influence of dynamic avalanche on paralleled IGBTs.