High-Speed and High-Security Hybrid AES-ECC Cryptosystem Based on FPGA

In the age of information, high-speed and high-security cryptosystems have become essential. This paper introduces a hybrid AES-ECC cryptosystem which takes advantages of Advanced Encryption Standard (AES) and Elliptic Curve Cryptography (ECC). In this cryptosystem, plaintext is encrypted by AES, which guarantees high encryption speed; meanwhile, by applying ECC to encrypt AES keys, the security of key distribution over insecure channels is greatly improved and key management becomes easier. To shorten latency, a six-clock-cycle Montgomery Ladder is applied in ECC core. In AES core, key expansion unit and SBOX are shared to conserve resources. The proposed crypto system is implemented on Xilinx Virtex-5 and the synthesize results shows that the cryptosystem is a cutting-edge design. The latency of the proposed architecture is optimized to
$10.04 \mu s$
(2,070 clock cycles) for encryption while
$10.44\mu s$
(2,153 clock cycles) for decryption with 206.2 MHz clock frequency at the cost of 23,764 LUTs. The throughput rates for encryption and decryption are 61.45 Mbps and 62.45 Mbps.