A 0.38-pJ/b Simplex and a 1.2-pJ/b Full-Duplex Chip-to-Chip Digital Communication Interface With Data Rate and Load Capacitance Adaptability

This work presents a simplex and a full-duplex digital communication interface in 65 nm CMOS that enhance the energy efficiency of chip-to-chip digital communication in low-speed low-power systems, e.g., for Internet-of-Things applications. A capacitive fully dynamic simplex interface is proposed first. A self-interference cancellation network is then applied to achieve full-duplex operation. Thanks to the all-dynamic architecture, the proposed interfaces allow efficient power scaling and can provide a BER of 5.10
^-12
. The simplex and full-duplex interfaces achieve an energy consumption of 0.38 and 1.2 pJ/b, respectively (with 19 pF load). The simplex interface achieves a power reduction of 2× to 27× compared to conventional low-voltage CMOS for data rates from 10 kb/s to 50 Mb/s. The full-duplex interface achieves a power reduction of 5× to 11× for data rates from 100 kb/s to 50 Mb/s.