A Novel Technique to improve Performance Evaluation of Domino Logic Circuits in CMOS and FinFET Technology

As the silicon industries miniaturizing the device size and increasing the performance day by day to implement more functionality in digital ICs. We will elaborate different techniques to put in to domino logic circuits. Power consumption can be minimize without deteriorating the performance circuit and efficiency of the circuit can be increases with proposed technique. Here we have use eight and sixteen input OR gates to calculate the UNG of the circuit with present and discussed design in Fin-FET and CMOS technology. With low power characteristics and great performance improvement in FinFET devices changes are obtained in higher I
_ON
/I
_oFF
ratio and the leakage current is reduced and it fastens the switching speed. Simulation is done on PTM 32nm process using H-spice C-2009.09-SP1 simulation tool by a 0.9 V dc supply. at 100MHz frequency. This work introduced a Low Power Stacked (LPS) FinFET based Domino logic 61.46% CKD, 49.08%, 29.18% DFD, 42.11% HSD, 29.36% SFD, saving of standby power of 18.79%, 46.15%,63.3%, in LP and SG mode of Fin-FET, for the 8 input OR gates.