Investigating the Highly Tolerant LDMOS Cell Array Design against the Negative Carrier Injection and the ESD Events

Optimum LDMOS array layout design is proposed which is tolerant against not only the negative carrier injection but also the ESD events. Both are indispensable features of the LDMOS, however, they have trade-off relation from cell array design point of view. Both characteristics are affected by N-guard ring resistance and its smaller value is better for negative carrier injection, but worse for ESD tolerance. The best structure in this study has increased allowable negative injection current by 40% compared to the reference structure, while TLP failure current (It
2
) degradation was suppressed to only 9%, and total area increase was kept to less than 15%.