Synthesis of FIR Filter using ADC-DAC: A FPGA Implementation

Finite Impulse Response (FIR) filters are one of the most widely used in FPGA implementations owing to its linear phase Property and stability. The main attention of FIR filter implementation is towards noise and performance constraints. This paper, deals on design 8 bit and 8 taps FIR filter for filtering of Noise level and band pass filter for stabilizing the frequency. Analog to Digital convertor (ADC) has been with input frequency of 500Hz, sampling frequency of 2000Hz and the amplitude of 1mV Peak to Peak, which is given to Field Programmable Gate array (FPGA), in which the FIR filtering operation takes place, which results in optimization of noise by 13% comparing to the internal noise from analog signal and consume time less time period of 13.42ns as compared to other active algorithm and the output from FPGA is fed to Digital to Analog Converter for verifying the original input signal.