A comparative study on the performance of 1S-1R and Complementary resistive switching models

Two prominent engineering solutions to mitigate sneak path current in Resistive random-access memory (RRAM) based cross bar arrays are a) one selector-one resistor (1S-1R) design and b) complementary resistive switching (CRS) device design. This paper presents the implementation and comparison of electrical models of 1S-1R as well as CRS device in 2×2 crossbar array and demonstrate the amount of sneak path current eliminated by both designs. To simulate the circuits, three write schemes are adopted such as floating, V/2 as well as V/3, with pulses of amplitude 4-4.5 V is applied to the selected cell for data write and 2-2.3 V is applied to perform read from the selected cell. In 1S-1R array, an initial SET pulse has been applied to obtain worst case state condition whereas in CRS device design, instead of applying initial SET pulses, an additional write back signal is applied to compensate for destructive read-0 process. From the simulation results, it has been revealed that write schemes such as floating and V/3 schemes are efficient to be used in CRS and 1S-1R memory designs. In V/3 scheme, the sneak path current originated during read process in 1S-1R based array is reduced by 96% whereas for CRS array shows 93% of reduction. Hence, it can be concluded that 1S-1R design outweigh CRS in mitigating the sneak path current in low dimension memory arrays.