A 0.3V, 625Mbps LVDS Driver in 0.18um CMOS Technology

This paper proposes an improved inverter by inserting a level shifter for low supply voltage. Before driving the transistor, the signal levels are shifted to beyond the supply voltage levels, thereby raising the gate overdrive voltage and the inverter bandwidth. In 0.18um CMOS process, the proposed inverter is used to design a 4-stage cascading pre-driver and a digitalized low-voltage differential-signaling (LVDS) driver, and the overall driver system occupied an active area of 0.0144mm². Under single 0.3V of supply voltage, the driver consumes a total current of 1.56mA. At 625Mbps, the output eye diagrams reveal 180ps (0.11UI) of peak jitter and 280mV of differential swing.