Possibilities of single-wafer single-lithography processing for nanoelectronic and optoelectronic VMMOS ULSI

3D nanoelectronic and optoelectronic vertical merged MOS (VMMOS & OVMMOS) elements increasing the ultra-high packaging density as a promising approach for advanced low-voltage high-speed ULSI have been proposed, analysed and simulated. Advanced single-wafer, single-lithography processing of the VMMOS and OVMMOS structures with combined channels for electrons and holes (generated by optical radiation in OVMMOS) offers a technology and economics (technonomics) advantage over standard CMOS and post-CMOS processing. Exploration and comparison of the minifab parameters (set-ups, processes and clean time processing), limits of cycle time for VMMOS, OVMMOS and planar CMOS processing show the significant advantage of the single-lithography processing strategy.