An 8b 1GS/s 2.55mW SAR-Flash ADC with Complementary Dynamic Amplifiers

An 8b SAR-Flash ADC is proposed, where four reset-power-free complementary dynamic amplifiers (CDAs) are first engaged to a 4b loop-unrolled (LU) SAR conversion and then reutilized for a 4.5b fine interpolating-flash conversion. The hardware-reusing flash ADC not only saves power consumption and area but also reduces the number of conversion cycles. A prototype 1GS/s ADC in 28nm CMOS achieves 45.5dB SNDR at a Nyquist input with 2.55mW power consumption, leading to a FoM
_Walden
of 16.6 fJ/c-s.