A Low Capture Power Oriented X-Identification-Filling Co-Optimization Method

High power dissipation can occur by high launch-induced switching activity when the response to a test vector is captured by flip-flops (FFs) in transition delay fault scan testing, resulting in excessive IR drop. Since excessive IR-drop significantly increases path delay, and thus might result in timing errors, such testing induces unnecessary yield loss in the deep submicron era. It is known that test manipulation methods using X-identification and X-filling are effective to reduce power dissipation in the capture cycle. Conventionally, these two techniques have been independently studied for a capture power dissipation problem. However, their effects depend on the application results of each other. In this paper, we propose an X-identification-filling method to co-optimize capture power dissipation using a Partial MaxSAT Solver. The method justifies values assigned to propagate target faults to pseudo primary outputs and reduces the number of transitions on as many internal signal lines as possible. Experimental results show that our proposed method reduced the numbers of capture-unsafe test vectors and unsafe faults compared with conventional methods.