Demonstration of a Low Latency (<20 ps) Fine-pitch (≤10 μm) Assembly on the Silicon Interconnect Fabric

We successfully demonstrate a fine-pitch (≤10 μm) assembly of functional dies on the Silicon-Interconnect Fabric (Si-IF) platform. Using the Simple Universal Parallel intERface on chips (SuperCHIPS) protocol, we experimentally show that the short links on Si-IF (≤500 μm) have a low latency of <; 20 ps for inter-die communication. In addition, we demonstrate a 4 Gbps/link data-transfer using the SuperCHIPS interface. This corresponds to an improvement of 10-50X in latency and 6-100X in data-bandwidth compared to conventional packaging technologies.