Warpage and Void Simulation of System in Package

The current trends of consumer electronics are to make the devices smaller, faster, better performance, and have more functions. To meet these requirements, semiconductor packaging is moving toward system-in-package (SiP) which is to pack a number of integrated circuits into a single module. In SiP applications, several chips or dies, containing integrated circuits, may be stacked vertically or horizontally to make the module very compact in size. The integrated circuits on different dies may connect to each other with either wire bonding or solder bumping technologies. For better electrical performance, instead of solder bumps, the flip chip technology has adapted copper bumps for their better electrical properties. Regardless of a myriad of the SiP applications, however, the void and warpage are still two of the most common reliability issues that are difficult to control and predict due to complex manufacturing parameters, design rules, and material properties [1]. Among the many manufacturing steps of SiP packages, encapsulation is one of the most important processing factors because the mold compound component not only has relatively high volume percentage compared to other components, it also effects the reliability of void and warpage [2]. This paper is to study the behaviors of warpage and void of SiP strips, with focuses on the processing steps of molding and inspection.