A Comparative Study of 2.5D and Fan-out Chip on Substrate : Chip First and Chip Last

The demand of integrated circuits (IC) of high band-width and high-performance applications (Networking, GPU) is more and stronger from end user. The heterogeneous integration techniques have been developed and widely used to integrate multi-chips with fine line/space interconnections. Several types of heterogeneous integration packaging techniques are offered in the market today, for example, through silicon via (TSV) interposer technology: 2.5D IC and re-distribution layer (RDL) fan-out process referred to as fan-out chip on substrate package (FOCoS). The fan-out techniques of FOCoS include chip first and chip last processes. In this study, FEA simulations are performed to examine the warpage, ELK layer crack risk, interconnection / RDL trace broken risk, and board level solder joint reliability of the thre package types include 2.5D IC, chip-first FOCoS and chip-last FOCoS. The validity of the simulation model is confirmed by comparing the numerical results for the warpage and thermal mechanical deformation of chip-last FOCoS with the experimental observations by advanced Metrology Analyzer (aMA) system. Further CFD simulations are then performed to investigate the heat dissipation performance of the three package types. It is clear from this study that these packages are very similar in form, format and function. The preliminary results have shown that high CTE polyimide to induce higher die to die (D2D) interconnection trace stress. This paper details the mechanical and thermal characteristics of the pros and cons would be deep understanding depend on different structure layouts and Bill of Material (BOM) selection.