Fine-Pitch Interconnection and Highly Integrated Assembly Packaging with FOMIP (Fan-out Mediatek Innovation Package) Technology

The market for mobile data access devices connected to a virtual cloud access point is exploding and driving both increased functional convergence as well as increased packaging complexity and sophistication. This is driving an unprecedented demand to increase the variety of advanced packages, such as chiplets and TSV (Through Silicon Via) interposer packaging solutions. It is expected that the industry will see more exciting interconnect technologies of advanced wafer level packaging such as TSV, 2.5D interposers, TSV-less (die last), eWLB (embedded Wafer Level Ball Grid Array)/FOWLP (Fan Out Wafer Level Package) to meet these needs. Because demands of die size reduction, efficiency enhancement and lower power consumption are always required in mobile communication applications with advanced Si node, much finer line width/space (LW/LS) and die pad pitch design is utilized. However, when the finer LW/LS design is used in the advanced Si node electronic devices, not only will there be an increased cost, but also the substrate manufacturing capability in a flip chip package must be considered. The substrate technology with finer LW/LS of 5/5μm and below currently is still a tough challenge in manufacturing. Therefore, in order to deliver a cost-efficient, fine pitch interconnection, highly integrated and performance packaging solution, the FOMIP (Fan-out Mediatek Innovation Package) technology is introduced in this paper. The FOMIP technology adopts 2.5D eWLB and flip chip package technologies with the design of 60μm die pad pitch, 5/5μm LW/LS and 1 layer redistribution layer (RDL) to extend the interconnection pitch as minimum 80μm by Cu pillar bumping process. The assembly challenges and process development including how to optimize the equipment handling and the warpage characterization of molded wafer is present. The warpage of molded wafer with Cu pillar bumps is collected to analyze different processes before eWLB package singulation. The molded eWLB package is adopted as a flip chip die to attach on a 2-layers embedded trace substrate (ETS) with LW/LS of 10/10μm by using cost-effective mass reflow (MR) chip attach process. To examine the quality and yield of the structure, package level long-term reliability tests are performed. Based on these results, it is believed that this examined FOMIP technology can be a robust, low profile and cost-effective package solution when much finer LW/LS and pitches in the die level design are utilized, such as 40μm die pad pitch with 2/2μm LW/LS and 1 layer RDL design and below.