Vertically Replaceable Memory Block Architecture for Stacked DRAM Systems by Wafer-on-Wafer (WOW) Technology

This article proposes a 3-D-based redundancy scheme for the stacked dynamic random-access memory (DRAM) systems, which enables highly efficient productivity with the wafer-on-wafer (WOW) technology. Vertically replaceable block scheme and redundantly added wafer stack(s) are the keys of this technique. Memory bank replacement of the vertical combinations is taken into consideration. Random defect yield loss, which is a fundamental barrier for both the WOW technology and the leading-edge technologies, is dealt with in this study. Not only 4, 8, and 12 layers, but also 17 (16+1), 25 (24+1), and 33 (32+1) layers can be targeted. Therefore, this technique makes the WOW technology as another system scaling enabler.