Dynamic Early Dirty Buffer Flush to Reduce Miss Penalty in Solid-State Drives

The design of high-performance solid-state drives (SSDs) have been conducted intensively for various server-based applications, and one of the most popular methods is to use internal memory as cache for NAND flash memory. This study aims to improve the average response time of I/O requests by reducing cache miss penalty. The main idea is to eliminate the dirty buffer flush time on a cache miss. Hence, the proposed policy preferentially replaces a clean buffer on a cache miss and reserves sufficient clean buffers by flushing dirty buffers in advance if the dirty buffers account for more than the threshold of the total buffers. This early flush is performed at an idle time to avoid interfering with foreground requests. The increase in NAND write operations, a side effect of the early flush, is limited by periodically adjusting the threshold considering the frequencies of a rewrite after the early flush and of a dirty buffer replacement. Consequently, the proposed policy reduces the average response time by 68.4%-92.0% compared with a CFLRU, with NAND writes increased by -0.4%-6.6%. Compared with a PRLRU, the average response time is reduced by 62.5%-92.0%, with NAND writes increased by 1.1%-6.9%. The result shows that the early flush can significantly improve the responsiveness of SSDs with nonvolatile memory or battery packed memory. A further analysis is required to verify the effect of early flush in SSDs with volatile memory.