A New Design of Phase-Locked Loop with Multiple Frequencies for Communication Standard

This paper presents a new design of Phase-Locked Loop (PLL) with multiple outputs in low power and high speed. The input 1Mhz - frequency of this PLL gotten external source is able to generate multiple frequencies provided for the circuits of communication standard in high speed Integrated Circuits, such as Serial Peripheral Interface (SPI - 128MHz), Two-wire Interface (I2C-Ultra fast mode 5Mhz), etc. The PLL is designed with a 90nm CMOS technology and verified under parasitic extraction. The results of this design are shown less than 1mW power consumption and the out range of 4Mhz to 128Mhz during 25-50°C temperature.