Parameter Extraction for a Simplified EKV-model in a 28nm FDSOI Technology

The gm/ID methodology is applicable for the circuit design in advanced nanometer technologies. This work proposes a systematic parameter extraction process for a simplified EKV-model with only three model parameters which is applicable to all CMOS technologies. The extraction procedure relies only on the drain current for a sweep of the gate voltage without the need of additional extraction simulations in SPICE or parameters from the model card. Therefore, it is independent from the applied technology or the compact model of the SPICE simulation. For devices with short channel lengths, three variations of the EKV model were evaluated which consider velocity saturation. The resulting model provides good results compared to the SPICE simulation over the complete operation region of the technology for long and short channel devices while keeping simplicity for fast tool-based circuit design procedures and hand calculations.