VLSI Design of a Squaring Architecture based on Yavadunam Sutra of Vedic Mathematics

In this digital epoch, the thirst for high speed is fulfilled by the accomplishment of digital multipliers. Multipliers play a fundamental role in many high-speed applications where the complex multiplications are carried out by squaring operations. Vedic Mathematics is a part of Atharva Veda which deals with the easiest methodology for all types of arithmetic calculations. Yavadunam is one of the squaring algorithms of Vedic Mathematics. But currently, there is a lack of implementation hardware for Yavadunam for squaring binary numbers. In this paper, a squaring architecture is designed by implementing Yavadunam algorithm. The design is simulated and realized with the help of Xilinx Spartan kit.