Investigation of DC Parameters of Double Gate Tunnel Field Effect Transistor (DG- TFET) for different Gate Dielectrics

In this research we focused to study the DC parameters of Double Gate Tunnel Field Effect Transistor (DGTFET). To overcome the major challenges faced by the conventional MOSFET, a silicon-based TFET device structure is constructed with SiO₂ as gate dielectric using TCAD simulator. The I_d-V_g characteristic of the device is plotted and various DC parameters are extracted. The DC parameters considered here are leakage current (I_off), driving current (I_on) and threshold voltage (V_t). The plot of electrostatic potential and electron barrier tunneling are also depicted. The same study is carried out for high κ-dielectrics like Silicon Nitride (Si₃N₄) and Hafnium Dioxide (HfO₂). The performance of DC parameters for various gate dielectrics is compared and studied.

I. INTRODUCTION

There are new challenges in the scaling of MOSFET and as per Moore's observation, the number of transistors doubles about every two years in a single chip. Continuing Moore’s law in the future is difficult because we can reduce the size of MOSFET up to a certain limit [1]. The result of scaling, short channel effects like Drain Induced Barrier Lowering (DIBL) increases leakage current. Furthermore, scaling in dimension demands for scaling of supply voltage to reduce power density and this demands a reduction in the threshold voltage to achieve device performance.